• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Exemplary embodiments of the present invention provide a method of growing a nitride semiconductor layer including growing a gallium nitride-based defect dispersion suppressing layer on a gallium nitride substrate including non-defect regions and a defect region disposed between the non-defect regions, and growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer.
    公开号:EP3680929A1
    申请号:EP20153397.3
    申请日:2013-11-28
    公开日:2020-07-15
    发明作者:Woo Chul Kwak；Seung Kyu Choi；Jae Hoon Song；Chae Hon Kim；Jung Whan JUNG
    申请人:Seoul Viosys Co Ltd；
    IPC主号:H01L21-00
    专利说明:
    [0001] Exemplary embodiments of the present invention relate to a method of growing a nitride semiconductor layer, a nitride semiconductor device, and a method of fabricating the same, and, more particularly, to a method of growing a nitride semiconductor layer on a growth substrate prepared using a tiling technique and a nitride semiconductor device and method of fabricating the same using the nitride semiconductor layer. DISCUSSION OF THE BACKGROUND
    [0002] Nitride semiconductors such as gallium nitride semiconductors may have a wide energy band gap and may be of a direct transition type. Nitride semiconductors may be used in fabrication of semiconductor devices, such as light emitting devices having a relatively short wavelength emission range, for example, ultraviolet, blue, and green light emitting devices, electronic devices, and the like.
    [0003] A nitride semiconductor layer may be grown on a heterogeneous substrate such as a sapphire substrate due to difficulty in preparation of a homogeneous substrate. However, the nitride semiconductor layer grown on the heterogeneous substrate may have a high-density of crystal defects such as thread dislocations, and thus not be suited for fabricating a device capable of being operated under high current density.
    [0004] Thus, techniques for preparing a nitride semiconductor layer using a homogeneous substrate, such as a gallium nitride substrate, as a growth substrate have been developed in recent years. For example, a bulk gallium nitride single crystal may be grown on a sapphire substrate via hydride vapor phase epitaxy (HVPE) and sliced to prepare a gallium nitride growth substrate.
    [0005] For mass production of semiconductor devices by growing a semiconductor layer on a substrate, it may be necessary for a growth substrate to have a relatively large size. Currently, a substrate used to fabricate optical devices such as light emitting diodes may have a size of 2 inches or more.
    [0006] A c-plane gallium nitride substrate may be obtained as a large substrate having a size of about 2 inches by slicing a bulk single crystal. However, it may be difficult to form semi-polar substrates or non-polar substrates, such as m-plane or a-plane gallium nitride substrates, to a size of 2 inches or more using the above method due to a limit on a growth plane or growth thickness. For this reason, studies based on non-polar or semi-polar gallium nitride substrates are mostly limited to growth of a nitride crystal using the non-polar or semi-polar substrate having a size of less than 1 inch, for example, having a maximum width of several millimeters or less.
    [0007] To provide a large-area growth substrate, a technique has been developed in which a plurality of seed substrates each having a desired crystal growth plane is arranged thereon and nitride semiconductor layers are then grown on the seed substrates, followed by slicing the grown nitride semiconductor layers.
    [0008] However, due to use of the plural seed substrates, a nitride crystal grown on a boundary line between the seed substrates may include a high density of crystal defects. In addition, a gallium nitride substrate prepared using the seed substrates may show a relatively large difference in off-angle depending upon a location due to a difference in crystal orientation between the seed substrates. Even though the off-angle and arrangement of the seed substrates may be controlled, it may be difficult to completely remove off-angle distribution on the gallium nitride substrate. Thus, a portion of the nitride crystal corresponding to a boundary region between the seed substrates may act as a defect source upon growth of the nitride semiconductor layer on the gallium nitride substrate.
    [0009] Moreover, a defect generated in the semiconductor layer may be transferred in a vertical direction, and also spread over a significantly wide area. As a result, it may be difficult to secure a semiconductor layer region capable of providing a semiconductor device exhibiting good properties, thereby decreasing productivity and yield. US 2003 020087 A1 , EP 2055811 A2 , WO 2008/048303 A2 and EP 0922792 A1 relate to nitride semiconductor devices of the prior art and methods for producing those devices. SUMMARY
    [0010] The invention relates to a method of growing a nitride semiconductor layer, the method comprising: (a) preparing the gallium nitride substrate by growing a gallium nitride crystal on seed substrates using hydride vapor phase epitaxy (HVPE), followed by slicing the gallium nitride crystal; (b) growing a gallium nitride-based defect dispersion suppressing layer on the gallium nitride substrate formed in step (a) using metal organic chemical vapor deposition; and (c) growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer, wherein the gallium nitride-based defect dispersion suppressing layer is a gallium nitride layer grown (1) at a temperature in the range of 900°C to 1000°C and grown at a pressure in a range from 100 torr to 400 torr, wherein the growth temperature of the defect dispersion suppressing layer is lower than the growth temperature of the gallium nitride semiconductor layer formed in step (c), and (2) at a growth rate which is slower than the gallium-nitride semi-conductor layer in step (c) and which is in the range from 1.5 µm/hr. to 2.5 µm/hr. Disclosed is also a method of growing a nitride semiconductor layer having good crystal quality using a gallium nitride substrate having a defect region as a growth substrate, and a method of fabricating the semiconductor device using the nitride semiconductor layer.
    [0011] Disclosed is also a method of growing a nitride semiconductor layer capable of preventing a defect region of a gallium nitride substrate ranging from spreading in a semiconductor layer grown on the substrate.
    [0012] Disclosed is also a method of fabricating a non-polar or semi-polar semiconductor device, which is mass producible at high yield.
    [0013] Additional features of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure.
    [0014] Disclosed is also a method of growing a nitride semiconductor layer, the method including growing a gallium nitride-based defect dispersion suppressing layer on a gallium nitride substrate comprising non-defect regions and a defect region disposed between the non-defect regions, and growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer.
    [0015] Disclosed is also a method of growing a gallium nitride substrate, the method including preparing the gallium nitride substrate by growing a gallium nitride crystal on seed substrates using hydride vapor phase epitaxy (HVPE), followed by slicing the gallium nitride crystal, growing a gallium nitride-based defect dispersion suppressing layer on the gallium nitride substrate using metal organic chemical vapor deposition, and growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer.
    [0016] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed
    [0017] The scope of the invention is defined solely by the claims. The use of the term "embodiment" in the description does not imply that the subject-matter in question forms part of the invention. BRIEF DESCRIPTION OF THE DRAWINGS
    [0018] The above and other aspects, features, and advantages of the present invention will become apparent from the detailed description of the following exemplary embodiments in conjunction with the accompanying drawings.Figure 1 shows schematic sectional views of a method of growing a nitride semiconductor layer according to an exemplary embodiment of thepresent invention. Figure 2 is a schematic sectional view of a nitride semiconductor layer grown without a defect dispersion suppressing layer (embodiment falling outside the scope of the invention). Figure 3(a) and Figure 3(b) are microscope images showing a surface of a semi-polar nitride semiconductor layer grown without a defect dispersion suppressing layer. Figure 4(a) and Figure 4(b) are microscope images showing surfaces of semi-polar nitride semiconductor layers on defect dispersion suppressing layers grown at relatively high and low temperatures, respectively. Figure 5(a) and Figure 5(b) are microscope images showing surfaces of semi-polar nitride semiconductor layers on defect dispersion suppressing layers grown at a relatively low temperature under different growth pressures, respectively. Figure 6 is a graph depicting PL intensities of six specimens of Figure 3(a), Figure 3(b), Figure 4(a), Figure 4(b), Figure 5(a), and Figure 5(b), respectively. Figure 7 is a microscope image showing a surface of a non-polar nitride semiconductor layer grown without a defect dispersion suppressing layer. Figure 8(a) and Figure 8(b) are microscope images showing surfaces of non-polar nitride semiconductor layers on defect dispersion suppressing layers grown at a relatively high temperature under different growth pressures, respectively. Figure 9 is an microscope image showing a surface of a non-polar nitride semiconductor layer on a dcfcct dispersion suppressing layer grown at a relatively low temperature. Figure 10 is a graph depicting PL intensities of four specimens of Figure 7, Figure 8(a), Figure 8(b), and Figure 9, respectively. DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
    [0019] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the present invention is not limited to the following exemplary embodiments and may be embodied in different ways, and that the exemplary embodiments are provided for complete disclosure and thorough understanding of the invention by those skilled in the art. In the drawings, the widths, lengths, thicknesses and the like of components may be exaggerated for convenience. Like components will be denoted by like reference numerals throughout the specification.
    [0020] Figure 1 shows schematic sectional views illustrating a method of growing a nitride semiconductor layer and a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention.
    [0021] Referring to Figure 1(a), a gallium nitride substrate 21 is prepared. The gallium nitride substrate 21 may be provided by growing a gallium nitride single crystal on a plurality of seed substrates using hydride vapor phase epitaxy, followed by slicing the gallium nitride single crystal.
    [0022] The gallium nitride substrate 21 includes a plurality of non-defect regions 21a corresponding to the plural seed substrates and at least one defect region 21b located between the non-defect regions 21a. Although the non-defect regions 21a may have the same growth plane, the non-defect regions 21a may have different off-angles. For example, the non-defect regions 21a may have a semi-polar or non-polar growth plane. In particular, the semi-polar growth plane may be, for example, (20-21) plane, and the non-polar growth plane may be an m-plane or a-plane. When the growth plane is an m-plane, the non-defect regions 21a has an off-angle with respect to [0001] direction, for example, from about -4° to about -10°, and may be from about -4° to -6°. At an off-angle from -4° to -10° with respect to the [0001] direction, the In content may he increased in an active layer.
    [0023] Referring to Figure 1(b), a gallium nitride-based defect dispersion suppressing layer 23 is grown on the substrate 21. The defect dispersion suppressing layer 23 may have the same composition as a semiconductor layer 25, for example, and may be formed of GaN, and may include Al and In in a composition ratio of less than 0.3. However, the defect dispersion suppressing layer 23 is grown under different process conditions from those of the semiconductor layer (for example, 25 of Figure 1(c)) to be grown thereon, and may be grown by metal organic chemical vapor deposition.
    [0024] The defect dispersion suppressing layer 23 is grown under different conditions from those of the semiconductor layer 25 to be grown thereon, for example, in terms of growth temperature, growth rate, growth pressure, and the like. In particular, the defect dispersion suppressing layer 23 is grown at a lower temperature than the semiconductor layer 25 to be grown thereon. The semiconductor layer 25 may be grown at a temperature exceeding 1000°C, and the defect dispersion suppressing layer 23 is grown at a temperature ranging from 900°C to 1000°C. In particular, the defect dispersion suppressing layer 23 may be grown at a temperature ranging from 960°C to 970°C. An optimum growth temperature for the defect dispersion suppressing layer 23 may slightly vary according to the growth plane of the gallium nitride substrate 21.
    [0025] In addition, the defect dispersion suppressing layer 23 is grown at a slower rate than the semiconductor layer 25 to be grown thereon. For example, the growth rate of the defect dispersion suppressing layer 23 may be about half that of the semiconductor layer 25, and ranges from 1.5 µm/hr to 2.5 µm/hr, and may be from 1.5 µm/hr to 2.0 µm/hr.
    [0026] The defect dispersion suppressing layer 23 is an epitaxial growth layer unlike a polycrystalline low temperature buffer layer formed on a heterogeneous substrate, such as a sapphire substrate. The defect dispersion suppressing layer 23 is grown while maintaining crystallinity of the substrate 21, and is grown to a thickness from 1 µm to 4 µm, and may be from 1.5 µm to 2.5 µm. The defect dispersion suppressing layer 23 may have a defect region 23b corresponding to the defect region 21b of the substrate 21. The defect region 23b may have a width similar to or narrower than that of the defect region 21b.
    [0027] The defect dispersion suppressing layer 23 may be grown under a growth pressure different from or the same as that of the semiconductor layer 25. The defect dispersion suppressing layer 23 is grown at a pressure ranging from 100 torr to 400 torr, and may be at about 150 torr. A volume ratio of H2 to a total gas is maintained within about 30%, and a growth process may be performed in a N2 atmosphere without use of H2.
    [0028] Referring to Figure 1(c), a gallium nitride semiconductor layer 30 is grown on the defect dispersion suppressing layer 23. According to the present exemplary embodiment, the gallium nitride semiconductor layer 30 may include a semiconductor layer that is an n-type contact layer 25, an active layer 27, and a p-type contact layer 29. However, the semiconductor layer 25 may alternatively be a p-type layer, and layer 29 may be an n-type layer. The gallium nitride semiconductor layer 30 may be grown via metal organic chemical vapor deposition.
    [0029] The n-type contact layer 25 may include, for example, n-type GaN, the active layer 27 may have a single or multi-quantum well structure, which includes an InGaN quantum well layer, and the p-type contact layer 29 may include p-type GaN. Each of the n-type and p-type contact layers 25, 29 may consist of a single layer or multiple layers. The n-type contact layer 25 may be grown at a temperature of 1000°C or more, and may be grown at a temperature ranging from 1000°C to 1030°C.
    [0030] According to the present exemplary embodiment, the defect dispersion suppressing layer 23 is grown between the substrate 21 and the n-type contact layer 25 under different conditions from those of the n-type contact layer 25, thereby preventing the defect region 21b in the substrate 21 from being dispersed into the semiconductor layer 30. As a result, a width of a defect region 30b in the semiconductor layer 30 can be controlled not to exceed two times the width of the defect region 21b in the substrate 21. Thus, a relatively wide non-defect region 30a can be secured, and a semiconductor device can be fabricated in high yield by forming a device separation region in the defect region 30b. That is, the defect region 30b may be disposed under the space between two semiconductor light emitting elements of the semiconductor device.
    [0031] Figure 2 is a schematic sectional view of a nitride semiconductor layer grown without the defect dispersion suppressing layer 23.
    [0032] Referring to Figure 2, there is a difference in that the defect dispersion suppressing layer 23 is not present on a substrate 21, as compared with Figure 1. In Figure 2, an n-type contact layer 25 is directly grown on the substrate 21.
    [0033] The defect region 21b in the substrate 21 is dispersed in the semiconductor layer 25, and thus is more dispersed in the active layer 27 and the p-type contact layer 29 thereon.
    [0034] As a result, the defect region 30b is widely formed on a surface of the nitride semiconductor layer 30, and the non-defect region 30a becomes narrow.
    [0035] Here, although the defect region 30b is illustrated as being symmetrically dispersed in the semiconductor layer 30, the defect region 30b may be dispersed more into one side depending on an off-angle.
    [0036] The defect dispersion suppressing layer 23 of Figure 1 prevents the defect region 30b from being dispersed into the semiconductor layer 30 as in Figure 2. In particular, the defect dispersion suppressing layer 23 prevents the defect region 21b from being dispersed into the n-type contact layer 25. (Growth of semi-polar semiconductor layer)
    [0037] Figures 3(a) and 3(b) are microscope images showing a surface of a semi-polar nitride semiconductor layer grown without a defect dispersion suppressing layer.
    [0038] As described in Figure 2, specimens of Figures 3(a) and 3(b) were prepared by directly growing an n-type GaN contact layer 25 on a gallium nitride substrate 21 having a (20-21) growth plane, followed by growing semiconductor layers including an active layer 27 and a p-type contact layer 29 thereon under the same conditions.
    [0039] In the specimens of Figures 3(a) and 3(b), a semiconductor layer 30 was grown under substantially the same conditions, and there is only a slight difference in growth temperature of the n-type contact layer 25. The n-type semiconductor layer 25 was grown at a rate of about 3 µm/hr and a pressure of about 150 torr. As shown in Figures 3(a) and 3(b), it can be confirmed that a defect region (shown as darker area) was dispersed over a wide area on the surface of the semiconductor layer 30 (shown as lighter area) when the semiconductor layer 30 was grown without a defect dispersion suppressing layer.
    [0040] Figures 4(a) and 4(b) are microscope images showing surfaces of semi-polar nitride semiconductor layers on defect dispersion suppressing layers grown at relatively high and low temperatures (1030°C and 970°C), respectively.
    [0041] Specimens of Figures 4(a) and 4(b) were prepared by growing a GaN defect dispersion suppressing layer 23 on a substrate 21 having a (20-21) growth plane, followed by growing a semiconductor layer 30 thereon in a similar manner as described with reference to Figure 1(b). The specimen of Figure 4(a) was prepared by growing the defect dispersion suppressing layer 23 at 1030°C and at a rate of about 1.8 µm/hr, followed by decreasing the temperature and growing the n-type semiconductor layer 25 at about 1000°C, and the specimen of Figure 4(b) was prepared by growing the defect dispersion suppressing layer 23 at about 970°C and at a rate of about 1.8 µm/hr, followed by increasing the temperature and growing the n-type semiconductor layer 25 at about 1000°C. Both the defect dispersion suppressing layers 23 had a growth pressure of 400 torr, and both the n-type semiconductors 25 had a growth rate of about 3 µm/hr and a growth pressure of 150 torr. Both the specimens of Figures 4(a) and 4(b) were grown to a thickness of about 0.8 µm.
    [0042] Referring to Figures 4(a) and 4(b), it can be confirmed that the surface quality of the semiconductor layer 30 (shown as lighter area) was improved by interposing the defect dispersion suppressing layer 23 between the substrate 21 and the semiconductor layer 30. In particular, it can be confirmed that the surface quality of the semiconductor layer 30 was improved, and that the width of the defect region 30b (shown as darker area) became narrow by decreasing the growth temperature of the defect dispersion suppressing layer 23 from 1030°C to 970°C.
    [0043] Figures 5(a) and 5(b) are microscope images showing surfaces of semi-polar nitride semiconductor layers on defect dispersion suppressing layers grown at a relatively low temperature (970°C) under different growth pressures (400 torr, 150 torr), respectively.
    [0044] A specimen of Figure 5(a) was prepared by growing the defect dispersion suppressing layer 23 and the semiconductor layer 30 under substantially the same conditions as in the specimen of Figure 4(b), except that the defect dispersion suppressing layer 23 had a thickness of about 1.5 µm, which is about two times the thickness of the defect dispersion suppressing layer 23 in the specimen of Figure 4(b). There is a difference between the specimens of Figures 5(a) and 5(b) in that the defect dispersion suppressing layer 23 was grown under the same pressure of about 150 torr as that of the n-type semiconductor layer 25 in the specimen of Figure 5(b).
    [0045] Referring to Figures 5(a) and 5(b), it can he confirmed that the surface quality of the semiconductor layer 30 (shown as lighter area) was improved by increasing the thickness of the defect dispersion suppressing layer 23 as compared with the specimen of Figure 4(b). Further, the surface quality can be further improved by adjusting the growth pressure.
    [0046] From the experimental results, dispersion of the defect region 30b can be suppressed by growing the defect dispersion suppressing layer 23 on the substrate 21 under different growth conditions from those of the n-type semiconductor layer 25. In particular, the width of the defect region 30b can be reduced by adjusting the growth temperature and/or the growth rate of the defect dispersion suppressing layer 23 to a lower value than the growth temperature and/or the growth rate of the n-type semiconductor layer 25, respectively.
    [0047] Figure 6 is a graph depicting PL intensities of six specimens of Figure 3(a), Figure 3(b), Figure 4(a), Figure 4(b), Figure 5(a), and Figure 5(b), respectively.
    [0048] Referring to Figure 6, it can be confirmed that PL intensity was improved as the surface quality of the semiconductor layer 30 was improved. In particular, when the defect dispersion suppressing layer 23 was interposed between the substrate 21 and the semiconductor layer 25, the PL intensity was increased as compared with the specimen free from the defect dispersion suppressing layer 23 even though the defect dispersion suppressing layer 23 was grown at a relatively high temperature (1030°C) as in the specimen 3 of Figure 4(a).
    [0049] Further, as in the specimen of Figure 5(a), the PL intensity may be improved by increasing the thickness of the defect dispersion suppressing layer 23 to about 1.5 µm while the growth temperature is adjusted to about 970°C, so the growth temperature of the dispersion suppressing layer 23 is lower than that of the n-type semiconductor layer 25. Thus, the PL intensity can be optimized by controlling the growth pressure. (Growth of non-polar semiconductor layer)
    [0050] Figure 7 is a microscope image showing a surface of a non-polar nitride semiconductor layer grown without a defect dispersion suppressing layer.
    [0051] As described in Figure 2, the specimen of Figure 7 was prepared by directly growing an n-type contact layer 25 on a gallium nitride substrate 21 having an m(10-10) growth plane, followed by growing semiconductor layers including an active layer 27 and a p-type contact layer 29 thereon.
    [0052] When the semiconductor layer 30 was grown without the defect dispersion suppressing layer 23, the semiconductor layer 30 had a rough surface, and that the defect region (shown as darker area) was dispersed over a wide area.
    [0053] Figures 8(a) and 8(b) are microscope images showing surfaces of non-polar nitride semiconductor layers 30 on GaN defect dispersion suppressing layers 23 grown at a relatively high temperature (1030°C) under different growth pressures (400 torr, 150 torr), respectively.
    [0054] Specimens of Figures 8(a) and 8(b) were prepared by growing the defect dispersion suppressing layer 23 on a substrate 21 having a (10-10) growth plane, followed by growing the semiconductor layer 30 thereon in a similar manner as described with reference to Figure 1(b). The specimen of Figure 8(a) was prepared by growing the defect dispersion suppressing layer 23 at 1030°C and about 400 torr and at a rate of about 2.5 µm/hr, followed by decreasing the temperature and growing the n-type semiconductor layer 25 at about 1000°C and at a rate of about 3 µm/hr. The specimen of Figure 8(b) was prepared in a similar manner as the specimen of Figure 8(a), although there was a difference in that the specimen of Figure 8(b) was grown at a pressure of 150 torr. The defect dispersion suppressing layer 23 was grown for about 50 minutes, and had a thickness of about 2.1 µm.
    [0055] Referring to Figures 8(a) and 8(b), it can be confirmed that the surface quality of the semiconductor layer 30 was improved by interposing the defect dispersion suppressing layer 23 between the substrate 21 and the semiconductor layer 30. In particular, the surface quality can be relatively improved by lowering the growth pressure to 150 torr.
    [0056] Figure 9 is a microscope image showing a surface of a non-polar nitride semiconductor layer 30 on a defect dispersion suppressing layer 23 grown at a relatively low temperature (960°C).
    [0057] In a specimen of Figure 9, the defect dispersion suppressing layer 23 and the semiconductor layer 30 were grown under substantially the same conditions as in the specimen of Figure 8(b), except that the defect dispersion suppressing layer 23 had a growth temperature of 960°C.
    [0058] Referring to Figure 9, the surface quality of the semiconductor layer 30 was improved by lowering the growth temperature of the defect dispersion suppressing layer 23 to 960°C.
    [0059] From the experimental results, the defect region 30b may be suppressed from being dispersed by growing the defect dispersion suppressing layer 23 on the substrate 21 under different growth conditions from those of the n-type semiconductor layer 25.
    [0060] Figure 10 is a graph depicting PL intensities of four specimens of Figure 7, Figure 8(a), Figure 8(b), and Figure 9.
    [0061] Referring to Figure 10, the PL intensity was improved as the surface of the semiconductor layer 30 was improved (that is, formation of defect regions was reduced). In particular, the PL intensity can be increased by lowering the growth pressure of the defect dispersion suppressing layer 23 to 150 torr as in the specimen of Figure 8(b). Further, the PL intensity can be further increased by lowering the growth temperature of the defect dispersion suppressing layer 23 to 960°C.
    [0062] According to exemplary embodiments of the present invention, a nitride semiconductor layer having good crystal quality can he grown using the gallium nitride substrate described above as the growth substrate, and thus, a non-polar or semi-polar semiconductor device providing high productivity and yield can be fabricated. In particular, according to exemplary embodiments of the present invention, a defect region of the gallium nitride substrate may be prevented from spreading into the nitride semiconductor layer grown on the gallium nitride substrate.
    [0063] Although the invention has been illustrated with reference to exemplary embodiments in conjunction with the drawings, it will be apparent to those skilled in the art that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention. Further, it should be understood that some features of a certain exemplary embodiment may also be applied to other exemplary embodiments without departing from the scope of the invention. Therefore, it should be understood that the exemplary embodiments are provided by way of illustration only and are given to provide complete disclosure of the invention and to provide thorough understanding of the invention to those skilled in the art. Thus, it is intended that the present invention cover the modifications and variations provided they fall within the scope of the appended claims.
    权利要求:
    Claims (12)
    [0001] A nitride semiconductor device, comprising:
    a gallium nitride substrate comprising non-defect regions and a defect region disposed between the non-defect regions;
    a gallium nitride-based defect dispersion suppressing layer disposed on the gallium nitride substrate; and
    a gallium nitride semiconductor layer disposed on the defect dispersion suppressing layer.
    [0002] The nitride semiconductor device of claim 1, wherein the gallium nitride semiconductor layer comprises:
    an n-type contact layer disposed on the defect dispersion suppressing layer;
    a p-type contact layer disposed on the n-type contact layer; and
    an active layer disposed between the n-type and p-type contact layers.
    [0003] The nitride semiconductor device of claim 2, wherein gallium nitride semiconductor layer further comprises a device separation region.
    [0004] The nitride semiconductor device of claim 3, wherein the defect region is disposed under the device separation region.
    [0005] The nitride semiconductor device of claim 3, wherein the device separation region comprises a space formed in the gallium nitride semiconductor layer, and the defect region is disposed entirely under the space.
    [0006] The nitride semiconductor device of claim 1, wherein the defect dispersion suppressing layer is 1 µm to 4 µm thick.
    [0007] The nitride semiconductor device of claim 1, wherein the gallium nitride substrate comprises a semi-polar or non-polar substrate, and the non-defect regions comprise different off-angles.
    [0008] The nitride semiconductor device of claim 1, wherein the defect dispersion suppressing layer is an epitaxial growth layer.
    [0009] The nitride semiconductor device of claim 1, wherein the defect dispersion suppressing layer has a defect region corresponding to the defect region of the gallium nitride substrate.
    [0010] The nitride semiconductor device of claim 9, wherein the defect dispersion suppressing layer has a width same as or less than that of the defect region of the gallium nitride substrate.
    [0011] The nitride semiconductor device of claim 1, wherein the gallium nitride semiconductor layer has a defect region coresponding to the defect region of the gallium nitride substrate.
    [0012] The nitride semiconductor device of claim 11, wherein the gallium nitride semiconductor layer has a width same as or less than 2 times the width of the defect region of the gallium nitride substrate.
    类似技术:
    公开号 | 公开日 | 专利标题
    US10177229B2|2019-01-08|Semiconductor material having a compositionally-graded transition layer
    US9691712B2|2017-06-27|Method of controlling stress in group-III nitride films deposited on substrates
    Marchand et al.2001|Metalorganic chemical vapor deposition of GaN on Si |: Stress control and application to field-effect transistors
    EP2641267B1|2020-03-18|Semiconductor wafer comprising gallium nitride layer having one or more silicon nitride interlayer therein
    TWI490918B|2015-07-01|Method for improved growth of semipolar |n
    KR100976268B1|2010-08-18|Method for growth of GaN single crystal, method for preparation of GaN substrate, process for producing GaN-based element, and GaN-based element
    US6635904B2|2003-10-21|Indium gallium nitride smoothing structures for III-nitride devices
    US6861271B2|2005-03-01|Forming indium nitride | and indium gallium nitride | quantum dots grown by metal-organic-vapor-phase-epitaxy |
    EP1796180B1|2017-06-07|Light emitting element and its manufacturing method
    EP0551721B1|1997-03-05|Gallium nitride base semiconductor device and method of fabricating the same
    US8207054B2|2012-06-26|Group III nitride semiconductor substrate, substrate for group III nitride semiconductor device, and methods of making same
    EP2102899B1|2020-11-11|Nitride nanowires and method of producing such
    US7157307B2|2007-01-02|Zn-base semiconductor light-emitting device and method for manufacturing same
    EP1997125B1|2017-11-15|Growth method using nanocolumn compliant layers and hvpe for producing high quality compound semiconductor materials
    EP1869707B1|2012-06-13|Technique for the growth of planar semi-polar gallium nitride
    US8390023B2|2013-03-05|Sapphire substrate, nitride semiconductor luminescent element using the sapphire substrate, and method for manufacturing the nitride semiconductor luminescent element
    KR101144466B1|2012-05-11|Method for manufacturing nitride semiconductor crystal layer
    EP2313543B1|2013-05-29|Growth of planarand semi-polar {1 1-2 2} gallium nitride with hydride vapor phase epitaxy |
    US20160319459A1|2016-11-03|METHOD FOR PRODUCING A TEMPLATE FOR EPITAXIAL GROWTH HAVING A SAPPHIRE | SUBSTRATE, AN INITIAL-STAGE AlN LAYER AND LATERALLY OVERGROWN AlxGayN | LAYER
    KR100674829B1|2007-01-25|Nitride based semiconductor device and method for manufacturing the same
    US6495894B2|2002-12-17|Photonic device, a substrate for fabricating a photonic device, a method for fabricating the photonic device and a method for manufacturing the photonic device-fabricating substrate
    US7435608B2|2008-10-14|III-V group nitride system semiconductor self-standing substrate, method of making the same and III-V group nitride system semiconductor wafer
    EP2019437B1|2018-07-11|Iii nitride compound semiconductor laminated structure
    US6716655B2|2004-04-06|Group III nitride compound semiconductor element and method for producing the same
    US8835983B2|2014-09-16|Nitride semiconductor device including a doped nitride semiconductor between upper and lower nitride semiconductor layers
    同族专利:
    公开号 | 公开日
    JP6306331B2|2018-04-04|
    KR102062381B1|2020-01-03|
    JP2014110431A|2014-06-12|
    US9728404B2|2017-08-08|
    EP2738793A1|2014-06-04|
    EP2738793B1|2020-03-04|
    KR20140070043A|2014-06-10|
    US9142622B2|2015-09-22|
    US20150380237A1|2015-12-31|
    US20140151713A1|2014-06-05|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2020-06-12| STAA| Information on the status of an ep patent application or granted ep patent|Free format text: STATUS: THE APPLICATION HAS BEEN PUBLISHED |
    2020-06-12| PUAI| Public reference made under article 153(3) epc to a published international application that has entered the european phase|Free format text: ORIGINAL CODE: 0009012 |
    2020-07-15| AC| Divisional application: reference to earlier application|Ref document number: 2738793 Country of ref document: EP Kind code of ref document: P |
    2020-07-15| AK| Designated contracting states|Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
    2021-01-15| STAA| Information on the status of an ep patent application or granted ep patent|Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
    2021-02-17| RBV| Designated contracting states (corrected)|Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
    2021-02-17| 17P| Request for examination filed|Effective date: 20210112 |
    优先权:
    申请号 | 申请日 | 专利标题
    [返回顶部]